Exemplary embodiments of the present invention relate to nonvolatile memory devices, and more particularly, a nonvolatile memory device and a method for driving the same.
Nonvolatile memory devices retain stored data even when power supply thereto is interrupted. Among the nonvolatile memory devices, a floating gate type nonvolatile memory device is being widely used. Here, the nonvolatile memory device is driven using a floating gate that is disposed on a channel region of a substrate and is insulated therefrom. Specifically, the nonvolatile memory device is controlled by shifting the threshold voltage of a memory cell by controlling the amount of charge retained in a conduction band of the floating gate.
When a program voltage is applied to the floating gate, the threshold voltage of the memory cell increases. Here, because of different physical characteristics of individual memory cells in a nonvolatile memory device, the memory cells may have threshold voltages variously ranging in a threshold voltage distribution range. Hereafter, a method for storing data in a memory cell will be described in the context of a flash memory device which is a floating gate type nonvolatile memory device.
A nonvolatile memory device includes a memory cell array that stores data. The memory cell array includes a plurality of memory blocks. Each of the memory blocks includes a plurality of pages. Each of the pages includes a plurality of memory cells. The memory cells are divided into on-cells and off-cells according to threshold voltage distributions. The on-cell is an erased cell and the off-cell is a programmed cell. The nonvolatile memory device performs an erase operation on a memory block by memory block basis and performs a read/write operation on a page by page basis.
Meanwhile, the nonvolatile memory device may store 1-bit data or more in a memory cell. In general, a memory cell storing 1-bit data is called a single-level cell (SLC) and a memory cell storing at least 2-bit data is called a multi-level cell (MLC). The SLC has an erase state and a program state according to threshold voltages. The MLC has an erase state and a plurality of program states according to threshold voltages.
FIG. 1 is a configuration diagram of a conventional nonvolatile memory device.
Referring to FIG. 1, a nonvolatile memory device includes a cell string 110, a bit line BL, a voltage transmission unit 120, and a page buffer 130. The cell string 110 includes a plurality of memory cells 111, 112 and 113 connected in series. The bit line BL is connected to the cell string 110. The voltage transmission unit 120 is configured to apply a voltage of the bit line BL to a sensing node SO in a verify operation, where the verify operation includes an evaluation operation for connecting a memory cell whose programmed state is to be verified with the bit line and a sensing operation for coupling the bit line and a sense node of a page buffer. The page buffer 130 is configured to determine a voltage of the sensing node SO in response to data stored therein before the verify operation, or to update the data to a logic value corresponding to a voltage level of the sensing node SO in the verify operation.
The cell string 110 means a string structure that is constructed by a series connection between a source select transistor SSL (a transistor receiving an SSL signal) and a drain select transistor (a transistor receiving a DSL signal). Various voltages are applied through a plurality of word lines WL0, WL1 and WLN to the floating gates of the memory cells 111, 112 and 113.
Hereafter, a program/verify operation of a nonvolatile memory device will be described with reference to FIG. 1. Hereafter, a cell to be programmed will be referred to as a target cell, and the program/verify operation will be described by assuming, as an example, that the first memory cell 111 is a target cell.
Program voltages are applied according to an Increment Step Pulse Program (ISPP) scheme. According to an ISPP scheme, a first program voltage is applied to the world line WL1 and a verify operation is performed thereon. As a result of the verify operation, if it is determined to not have been sufficiently programmed, a second program voltage higher than the first program voltage is applied thereto and a verify operation is performed thereon. Repeating an operation of applying a program voltage (hereinafter referred to as a program operation) and an operation of verifying a program pass/fail of the target cell 111, by gradually increasing the program voltage for a subsequent operation, until the target cell 111 is programmed, is called an ISPP scheme.
The verify operation is performed in the following order. The sensing node SO is precharged by the page buffer 130 to a precharge voltage VCC. A precharge bias is applied to the voltage transmission unit 120 to electrically connect the sensing node SO and the bit line BL, and a voltage of the sensing node SO is transmitted to the bit line BL to precharge the bit line BL (“a bit line precharge operation”).
When the bit line BL is precharged, a verify voltage is applied to the target cell 111. The verify voltage is to verify a program pass/fail of the target cell 111. A turn-on/pass voltage (that is, a voltage for turning on a transistor) is applied to the floating gates of the other memory cells 112 and 113. If the target cell 111 is programmed, the bit line BL maintains the precharge voltage VCC; and if the target cell 111 is not programmed, the voltage of the bit line BL decreases (“an evaluation operation”).
After completion of the evaluation operation, the voltage of the bit line BL indicates the program pass/fail of the target cell 111. A sensing bias is applied to the voltage transmission unit 120 to electrically connect the bit line BL and the sensing node SO, and the voltage of the bit line BL is transmitted to the sensing node SO. The data stored in the page buffer 130 is updated to a data value corresponding to a voltage level of the sensing node SO in a sensing operation.
In the case of 4 KB (kilo byte) memory page, one page includes about 32,000 (4×1024×8) memory cells. Thus, in a program operation, according to the characteristics of memory cells, some memory cells may be program-passed cells and some memory cells may be program-failed cells. In the case of a nonvolatile memory device including multi-level cells, the memory cell of a low target threshold voltage is programmed first and then the memory cell of a high target threshold voltage is programmed. Here, the memory cell having a program/verify operation completed does not requires a precharge of the bit line BL for a verify operation. Conventionally, all bit lines BL included in a page are precharged before the verify operation regardless of whether a program/verify operation on some memory cells is completed. It is useful to reduce a large peak current flowing in the nonvolatile memory device during the bit line (BL) precharge operation and thus, reduce power consumption.